Hello world!
Welcome to WordPress. This is your first post. Edit or delete it, then start writing!
Welcome to WordPress. This is your first post. Edit or delete it, then start writing!
// lab 3 module Freq_Selector(input clk ,rst , ld , input [3:0] par_load ,output co); reg [8:0] counter ; reg [3:0] hard_coded = 4’b1010; reg load ; always @(posedge clk , posedge rst , posedge load) begin if(rst) counter <= 9’b0; else if(load) counter <= {par_load, hard_coded}; else counter <= counter + 1; end assign…
Details